DocumentCode
1650630
Title
NBTI mitigation by optimized NOP assignment and insertion
Author
Firouzi, Farshad ; Kiamehr, Saman ; Tahoori, Mehdi B.
Author_Institution
Dependable Nano-Comput. (CDNC), Karlsruhe Inst. of Technol. (KIT), Karlsruhe, Germany
fYear
2012
Firstpage
218
Lastpage
223
Abstract
Negative Bias Temperature Instability (NBTI) is a major source of transistor aging in scaled CMOS, resulting in slower devices and shorter lifetime. NBTI is strongly dependent on the input vector. Moreover, a considerable fraction of execution time of an application is spent to execute NOP (No Operation) instructions. Based on these observations, we present a novel NOP assignment to minimize NBTI effect, i.e. maximum NBTI relaxation, on the processors. Our analysis shows that NBTI degradation is more impacted by the source operands rather than instruction opcodes. Given this, we obtain the instruction, along with the operands, with minimal NBTI degradation, to be used as NOP. We also proposed two methods, software-based and hardware-based, to replace the original NOP with this maximum aging reduction NOP. Experimental results based on SPEC2000 applications running on a MIPS processor show that this method can extend the lifetime by 37% in average while the overhead is negligible.
Keywords
CMOS integrated circuits; MOSFET; ageing; integrated circuit reliability; CMOS technology; MIPS processor; NBTI degradation; NBTI mitigation; NBTI relaxation; NOP assignment; instruction opcodes; maximum aging reduction NOP; negative bias temperature instability mitigation; optimized NOP assignment; optimized NOP insertion; Degradation; Delay; Hazards; Logic gates; Program processors; Registers; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Conference_Location
Dresden
ISSN
1530-1591
Print_ISBN
978-1-4577-2145-8
Type
conf
DOI
10.1109/DATE.2012.6176465
Filename
6176465
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