Feasibility study of 70nm pitch Cu/porous low-k D/D integration featuring EUV lithography toward 22nm generation

Author

Nakamura, N. ; Oda, N. ; Soda, E. ; Hosoi, N. ; Gawase, A. ; Aoyama, H. ; Tanaka, Y. ; Kawamura, D. ; Chikaki, S. ; Shiohara, M. ; Tarumi, N. ; Kondo, S. ; Mori, I. ; Saito, S.

Author_Institution

Semicond. Leading Edge Technol., Inc., Tsukuba, Japan

fYear

2009

Firstpage

1

Lastpage

4

Abstract

A feasibility study of 70 nm pitch 2-level dual damascene interconnects featuring EUV lithography is presented. Using Ru barrier metal and scalable porous silica (Po-SiO, k=2.1), a low resistivity below 4.5 Â¿Â¿cm and a 13% reduction in wiring capacitance compared with porous SiOC (k=2.65) was obtained. The predicted circuit-performance using Po-SiO was 10% higher than that with porous SiOC. The electromigration reliability in 22 nm generation was consistent with the previous generations. The merit of EUV lithography on circuit design was also clarified.

Keywords

CMOS integrated circuits; capacitance; copper; electrical resistivity; electromigration; integrated circuit design; integrated circuit interconnections; integrated circuit reliability; nanolithography; porous materials; ruthenium; silicon compounds; ultraviolet lithography; 2-level dual damascene interconnects; CMOS; EUV Lithography; Ru; SiO; barrier metal; circuit design; electromigration reliability; resistivity; scalable porous silica; size 22 nm; size 70 nm; wiring capacitance; Conductivity; Delamination; Electrical capacitance tomography; Electromigration; Etching; Filling; Integrated circuit interconnections; Lithography; Silicon compounds; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424271

Filename

5424271