Title :
Top-gated FETs/inverters with diblock copolymer self-assembled 20 nm contact holes
Author :
Chang, Li-Wen ; Lee, T.L. ; Wann, Clement H. ; Chang, C.Y. ; Wong, H. S Philip
Author_Institution :
Center for Integrated Syst., Stanford Univ., Stanford, CA, USA
Abstract :
We have fabricated FETs and CMOS inverters with 20 nm contact holes patterned using self-assembled diblock copolymer. Alignment of the self-assembled contact holes to the MOSFET source and drain is achieved with a guiding layer. The self-assembly process is integrated with an existing CMOS process flow using conventional tools on a full wafer level. This is the first demonstration of functional circuits fabricated using self-assembly at the (n+1)th patterning level where n ¿ 1.
Keywords :
CMOS integrated circuits; atomic layer deposition; field effect transistors; invertors; lithography; polymer blends; self-assembly; CMOS inverters; CMOS process flow; field effect transistors; interlayer dieletric deposition; patterning level; self-assembled contact holes; self-assembled diblock copolymer; size 20 nm; Annealing; CMOS technology; Contacts; Costs; FETs; Inverters; Lithography; Materials science and technology; Printing; Self-assembly;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424272
