1650710

Evaluation on efficient measurement setup for transient-induced latchup with bi-polar trigger

Ker, Ming-Dou ; Hsu, Sheng-Fu

Nanoelectron. & Gigascale Syst. Lab., Nat. Chiao Tung Univ., Hsinchu, Taiwan

2005

121

128

CMOS integrated circuits; integrated circuit measurement; integrated circuit reliability; thyristors; transient response; 0.25 micron; CMOS IC reliability; SCR; TLU immunity; current-blocking diode; current-limiting resistance; electrical over-stress damage; ring oscillator test circuit; transient-induced latchup measurement; underdamped bi-polar trigger; CMOS technology; Circuit testing; Current measurement; Diodes; Electrical resistance measurement; Electromagnetic interference; Electrostatic discharge; Ring oscillators; Thyristors; Voltage;

English

ieee

Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

0-7803-8803-8

conf

10.1109/RELPHY.2005.1493073

1493073