1650762

Latchup in merged triple well structure

Voldman, S. ; Gebreselasie, E. ; Zierak, Michael ; Hershberger, D. ; Collins, D. ; Feilchenfeld, N. ; St Onge, S. ; Dunn, J.

IBM Microeletronics, Essex Junction, VT, USA

2005

129

136

BiCMOS integrated circuits; CMOS integrated circuits; MOSFET; electrostatic discharge; isolation technology; semiconductor device measurement; semiconductor device models; semiconductor device reliability; ESD; RF BiCMOS; RF CMOS; SiGe; dual-well structures; isolated MOSFET; isolating buried layers; latchup measurements; merged triple well structure latchup; BiCMOS integrated circuits; CMOS technology; Circuit noise; Germanium silicon alloys; Isolation technology; MOSFETs; Noise reduction; Radio frequency; Silicon germanium; Substrates;

English

ieee

Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

0-7803-8803-8

conf

10.1109/RELPHY.2005.1493074

1493074