Control system design realization via VHDL-A: requirements

Recent additions to Analog HDL specifications, the IEEE 1076.1 VHDL-AMS language standard, have raised the question as to whether the new additions provide sufficient capability for control system design. Control systems design is typically performed using signal flow based CAE packages. This paper describes the interface requirements between these packages and VHDL-AMS. Important issues concerning simulation control, model interface definitions and user interfaces are presented. The intent is to foster discussion and hopefully coordination between the control system design package vendors and the vendors of packages that support Analog HDLs