• DocumentCode
    1650770
  • Title

    Latch-up in 65nm CMOS technology: a scaling perspective

  • Author

    Boselli, G. ; Reddy, Vijay ; Duvvury, Charvaka

  • Author_Institution
    Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA
  • fYear
    2005
  • Firstpage
    137
  • Lastpage
    144
  • Keywords
    CMOS integrated circuits; integrated circuit reliability; sensitivity analysis; 130 nm; 180 nm; 65 nm; 90 nm; CMOS reliability; CMOS scaling; CMOS technology nodes; high current behavior; intrinsic latch-up process sensitivity; low-power applications; CMOS process; CMOS technology; Conductivity; Costs; Instruments; Isolation technology; Power supplies; Silicon; Thyristors; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International
  • Print_ISBN
    0-7803-8803-8
  • Type

    conf

  • DOI
    10.1109/RELPHY.2005.1493075
  • Filename
    1493075
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1650770