Title :
Latch-up in 65nm CMOS technology: a scaling perspective
Author :
Boselli, G. ; Reddy, Vijay ; Duvvury, Charvaka
Author_Institution :
Silicon Technol. Dev., Texas Instrum. Inc., Dallas, TX, USA
Keywords :
CMOS integrated circuits; integrated circuit reliability; sensitivity analysis; 130 nm; 180 nm; 65 nm; 90 nm; CMOS reliability; CMOS scaling; CMOS technology nodes; high current behavior; intrinsic latch-up process sensitivity; low-power applications; CMOS process; CMOS technology; Conductivity; Costs; Instruments; Isolation technology; Power supplies; Silicon; Thyristors; Voltage;
Conference_Titel :
Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International
Print_ISBN :
0-7803-8803-8
DOI :
10.1109/RELPHY.2005.1493075
