1650789

Latchup and the domino effect

Voldman, Steven H.

IBM Microeletronics, Essex Junction, VT, USA

2005

145

156

CMOS logic circuits; substrates; CMOS latchup stability condition; circuit logic disturbances; domino effect; external CMOS latchup; integrated circuits; minority carrier injection sources; secondary injections; semiconductor chips; substrate region; CMOS logic circuits; Cables; Electrostatic discharge; Error analysis; Fault location; Local area networks; Maintenance engineering; Reliability engineering; Substrates; Voltage;

English

ieee

Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

0-7803-8803-8

conf

10.1109/RELPHY.2005.1493076

1493076