The design of a symbiotic scalar-systolic array processor: SSSAP

The architecture of a scalar-systolic array processor which is suitable for image processing is presented. Unlike other attached array processors, the systolic array in the design is an integral part of the main processor. The systolic portion of the processor is treated as an array of arithmetic logic units (ALUs), and it is controlled in very much the same way as a scalar ALU. The goal of this project is to design a novel processor that is capable of real-time image processing using off-the-shelf components. The architecture and the performance of this machine are discussed