A configurable multiprocessor system for DSP behavioral simulation

Author

Koh, Wook ; Yeung, Ayred ; Hoang, Phu ; Rabaey, Jan

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1989

Firstpage

1403

Abstract

SMART, a multiprocessor architecture optimized for real-time behavioral simulation of digital signal processing (DSP) systems, is presented. The first prototype, currently under development, contains eight processors (peak 160 MFLOPS). The number of processors will be increased to 64 (peak 1.28 GFLOPS) in the future. The SMART system features a configurable bus and bypass units to improve the bandwidth of a single shared bus by taking advantage of the local communication between processors. Write queues and a distributed shared-memory system are provided to overlap the interprocessor communication with the processor computation, thereby making interprocessor communication delays almost invisible. Barrier synchronization, which is frequently used in DSP algorithms, is supported by hardware to yield low synchronization overhead

Keywords

computer interfaces; computerised signal processing; parallel architectures; parallel machines; pipeline processing; real-time systems; 160 MFLOPS; DSP behavioral simulation; SMART; barrier synchronisation; bypass units; configurable bus; configurable multiprocessor system; digital signal processing; distributed shared-memory system; low synchronization overhead; multiprocessor architecture; parallel processing; pipeline processing; real-time; single shared bus; write queues; Computer architecture; Concurrent computing; Digital signal processing; Echo cancellers; Hardware; Multiprocessing systems; Parallel processing; Performance analysis; Pipeline processing; Time measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100619

Filename

100619