A non-iterative compact model for carbon nanotube FETs incorporating source exhaustion effects

Because of high carrier velocities and quasi-ballistic transport properties, carbon-based (nanotube, graphene) field effect transistors (CNFETs) are considered to be potential candidates to replace CMOS in future technology generations . Most prior modeling of CNFETs has involved complex models, such as NEGF , but to properly evaluate these devices in circuits and systems, efficient compact models are required. In this paper, a fully analytical model based on ballistic transport and careful analysis of quantum capacitances is developed. This model requires neither iteration nor numeric integration. The model agrees well with numerical simulation and, in the limit of good contacts, predicts that a new effect, source exhaustion (using up all available carriers in the source), should limit the current. The model has also been integrated into a system level design optimization program which evaluates optimal device parameters based on system-level design objectives. The CNFET is projected to achieve 5× chip-level speed up over PDSOI at 11 nm technology node for a high-performance four-core processor with 1.5M logic gates.