• DocumentCode
    1651056
  • Title

    VaMV: Variability-aware Memory Virtualization

  • Author

    Bathen, Luis Angel D ; Dutt, Nikil D. ; Nicolau, Alex ; Gupta, Puneet

  • Author_Institution
    Sch. of Inf. & Comput. Sci., Univ. of California, Irvine, CA, USA
  • fYear
    2012
  • Firstpage
    284
  • Lastpage
    287
  • Abstract
    Power consumption variability of both on-chip SRAMs and off-chip DRAMs is expected to continue to increase over the next decades. We opportunistically exploit this variability through a novel Variability-aware Memory Virtualization (VaMV) layer that allows programmers to partition their application´s address space (through annotations) into virtual address regions and create mapping policies for each region. Each policy has different requirements (e.g., power, fault-tolerance) and is exploited by our dynamic memory management module (VaMVisor), which adapts to the underlying hardware, prioritizes the memory resources according to their characteristics (e.g., power consumption), and selectively maps data to the best-fitting memory resource (e.g., high-utilization data to low-power memory space). Our experimental results on embedded benchmarks show that VaMV is capable of reducing dynamic power consumption by 63% on average while reducing total execution time by an average of 34% by exploiting: 1) SRAM voltage scaling, 2) DRAM power variability, and 3) Efficient dynamic policy-driven variability-aware memory allocation.
  • Keywords
    DRAM chips; SRAM chips; power aware computing; resource allocation; virtual storage; DRAM power variability; SRAM voltage scaling; VaMV; VaMVisor; application address space; best-fitting memory resource; dynamic memory management module; dynamic policy-driven variability-aware memory allocation; dynamic power consumption reduction; execution time reduction; mapping policy; off-chip DRAM; on-chip SRAM; power consumption variability; variability-aware memory virtualization; virtual address region; Dynamic scheduling; Hardware; Memory management; Power demand; Random access memory; Resource management; System-on-a-chip;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
  • Conference_Location
    Dresden
  • ISSN
    1530-1591
  • Print_ISBN
    978-1-4577-2145-8
  • Type

    conf

  • DOI
    10.1109/DATE.2012.6176479
  • Filename
    6176479