Information Theoretic Approach to Address Delay and Reliability in Long On-Chip Interconnects

With shrinking feature size and growing integration density in the deep sub-micron technologies, the global buses are fast becoming the "weakest-links" in VLSI design. They have large delays and are error-prone. Especially, in system-on-chip (SoC) designs, where parallel interconnects run over large distances, the effects of crosstalk are detrimental to the overall system performance due to the large delays and un-reliability involved. This paper presents an information theoretic approach to address delay and reliability in long interconnects. A framework to calculate the capacity of a physical wire is laid out herein. The results for 8-bit wide buses of varying lengths in 0.1/mum technology are also presented. The wires are modeled based on their calculated parasitic (R,L,C) values and the coupling (C,L) parameters. Using this model, results are obtained for the data transfer capacity of long interconnects. It is seen that for wide buses, the signal delay distribution has a long tail, meaning that most signals arrive at the output much faster than the worst case delay. Using communication-theory, these "good" signals arriving early can be used to predict/correct the "few" signals arriving late. Further, results show that for every bus configuration, there exists an optimal frequency of transmission that will result in the maximum data transfer rate. Also, this optimal frequency is higher than the pessimistic worst case delay based clock design