1651145

A CMOS design style for logic circuit hardening

Zhang, Ming ; Shanbhag, Naresh R.

Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA

2005

223

229

CMOS logic circuits; combinational circuits; flip-flops; integrated circuit design; logic gates; radiation hardening (electronics); sequential circuits; transients; CMOS design style; charge collection efficiency; clock distribution network; combinational circuits; critical charge value; drain-body junctions; dynamic CMOS circuits; hardened D-latch; inverter chain; isolated wells; logic circuit hardening; radiation-induced single event transients; soft error rate; source terminals; source-body junctions; static CMOS circuits; voltage division; CMOS logic circuits; Clocks; Degradation; Error analysis; Inverters; Logic arrays; Logic circuits; Neutrons; Resistors; Sequential circuits;

English

ieee

Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

0-7803-8803-8

conf

10.1109/RELPHY.2005.1493088

1493088