HEPWM implementation for fifteen level cascaded inverter using field programmable gate array

Inverters are considered an integral part in renewable energy systems. However, the presence of harmonics in their output leads to severe effect on the performance of the systems connected to them. Recently, the multilevel voltage source inverter (MVSI) has been used extensively for high power conversion. It has better harmonics profile than the two-level VSI. The harmonics elimination pulse width modulation (HEPWM) method has been widely applied to remove low frequency harmonics from the output voltage of MVSI. In this paper, implementation of HEPWM using field programmable gate array (FPGA) was done to generate trigering pulses for fifteen levels cascaded inverter. The experimental verification is carried out by constructing the fifteen level MVSI using the Altera FPGA. In addition, comparison is made with MATLAB/Simulink results. It is found that both simulation and hardware results are in very close agreement with the theoretical expectation.