A low jitter 1.25 GHz CMOS analog PLL for clock recovery

Conventional PLL design techniques used to implement CMOS GHz range clock recovery circuits typically suffer from significant power supply coupled noise in large integrated systems. This noise worsens the jitter of the PLL and degrades the system Bit-Error-Rate (BER). This paper describes an analog approach which applies the fully differential current steering technique throughout the whole PLL system in order to reject supply coupled noise. Moreover, since this circuit works at reduced voltage swing, it not only has the potential of operating at very high frequency but also dissipates less power at high frequencies than conventional CMOS logic. Simulation results show that this clock recovery circuit can work at 1.25 GHz with power dissipation of less than 100 mW. Jitter of the proposed structure is about 40% of that of digital single-ended PLL clock recovery circuits. All the simulations are based on HP 0.5 μm N-well CMOS single-poly triple-metal technology