Timing-Driven Placement for Heterogeneous Field Programmable Gate Array

In this paper, a new timing-driven placement algorithm is proposed to handle complicated placement requirements inherent in FPGAs with heterogeneous resources (dedicated logic block, memory block). The new algorithm employs a multi-layer density system with each layer modeling a drastically different architectural resource. By introducing the multi-layer density system, a heterogeneous placement task is translated to a set of homogeneous ones, with each of them being handled at a different density layer. We also present a new iterative timing optimization scheme which is seamlessly integrated in the placement process. The tight interaction between the placement and timing optimization produces superior timing results for industrial designs