DocumentCode
1651474
Title
Timing Model Reduction for Hierarchical Timing Analysis
Author
Zhou, Shuo ; Zhu, Yi ; Hu, Yuanfang ; Graham, Ronald ; Hutton, Mike ; Chung-kuan Cheng
fYear
2006
Firstpage
415
Lastpage
422
Abstract
In this paper, we propose a timing model reduction algorithm for hierarchical timing analysis based on a biclique-star replacement technique. In hierarchical timing analysis, each functional block is characterized into an abstract timing model. The complexity of analysis is linear to the number of edges in the abstract timing model for timing propagation. We propose a biclique-star replacement technique to minimize the number of edges in the timing model. The experiments on industry test cases show that by allowing acceptable errors, the proposed algorithm can largely reduce the number of edges in the timing model
Keywords
graph theory; network synthesis; timing; abstract timing model; biclique-star replacement; hierarchical timing analysis; timing model reduction; Added delay; Algorithm design and analysis; Computer science; Delay effects; Delay lines; Field programmable gate arrays; Permission; Reduced order systems; Testing; Timing; Biclique-star Replacement; Hierarchical Timing Analysis;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on
Conference_Location
San Jose, CA
ISSN
1092-3152
Print_ISBN
1-59593-389-1
Electronic_ISBN
1092-3152
Type
conf
DOI
10.1109/ICCAD.2006.320150
Filename
4110207
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