A pipelined architecture for a high speed digital oscillator

In this paper, an implementation of a digital oscillator using advanced digital arithmetic techniques is proposed. A pipelined architecture is exploited in the implementation of the oscillator. The impact of using pipelining on the performance of the digital oscillator is studied and compared with non-pipelined structures. The synthesis results show that the proposed structure with pipelining is superior to the structure without pipelining in terms of the maximum frequency attained.