Benchmarking the device performance at sub 22 nm node technologies using an SoC framework

Author

Shrivastava, Mayank ; Verma, Bhaskar ; Baghini, M. Shojaei ; Russ, Christian ; Sharma, Dinesh Kumar ; Gossner, Harald ; Rao, V. Ramgopal

Author_Institution

Dept. of Electr. Eng., Indian Inst. of Technol.-Bombay, Mumbai, India

fYear

2009

Firstpage

1

Lastpage

4

Abstract

For the first time this paper makes an attempt at predicting the System-on-Chip (SoC) performance (i.e. logic, SRAM, ESD and I/O) of various sub 20 nm channel length planar and non-planar SOI devices using extensive & well calibrated 3D device and mixed-mode TCAD simulations. It has been shown that the non-planar devices such as FinFETs are not the ideal choice for SoC applications and perform poorly in comparison to the Ultra thin body (UTB) planar SOI MOSFETs. We further show different strategies to optimize the planar UTB MOSFETs for improved ESD robustness and I/O performance.

Keywords

MOSFET; SRAM chips; electrostatic discharge; logic circuits; silicon-on-insulator; system-on-chip; technology CAD (electronics); 3D device; ESD robustness; FinFET; I/O performance; SoC framework; channel length planar; mixed-mode TCAD simulations; nonplanar SOI devices; nonplanar devices; planar UTB MOSFET; size 22 nm; system-on-chip performance; ultra thin body planar SOI MOSFET; Delay; Electrostatic discharge; FinFETs; Integrated circuit interconnections; Inverters; Logic devices; MOSFETs; Nanoscale devices; Random access memory; Robustness;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424311

Filename

5424311