DocumentCode :
1651939
Title :
Soft Error Derating Computation in Sequential Circuits
Author :
Asadi, Hossein ; Tahoori, Mehdi B.
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA
fYear :
2006
Firstpage :
497
Lastpage :
501
Abstract :
Soft error tolerant design becomes more crucial due to exponential increase in the vulnerability of computer systems to soft errors. Accurate estimation of soft error rate (SER), the probability of system failure due to soft errors, is a key factor in design of cost-effective soft error resilient systems. We present a very fast and accurate approach based on enhanced static timing analysis and signal probabilities to estimate the probability of latching an incorrect value in the system bistables (timing derating). Experimental results and comparison with fault injections using timing accurate Monte-Carlo simulations show that the accuracy of our approach is within 1% while orders of magnitude faster
Keywords :
Monte Carlo methods; estimation theory; logic design; probability; sequential circuits; Monte-Carlo simulation; computer systems; latching probability estimation; sequential circuits; signal probabilities; soft error rate; soft error tolerant design; static timing analysis; CMOS technology; Circuit faults; Computer errors; Error analysis; Flip-flops; Logic; Sequential circuits; Signal analysis; Single event transient; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA
ISSN :
1092-3152
Print_ISBN :
1-59593-389-1
Electronic_ISBN :
1092-3152
Type :
conf
DOI :
10.1109/ICCAD.2006.320164
Filename :
4110221
Link To Document :
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