DocumentCode

1651978

Title

Optimal Seguencing of Scan Registers

Author

Narayanan, Sridhar ; Njinda, Charles ; Breuer, Melvin

fYear

1992

Firstpage

293

Keywords

Circuit testing; Costs; Degradation; Design for testability; Flip-flops; Hardware; Multiplexing; Pins; Registers; Test equipment;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1992. Proceedings., International

ISSN

1089-3539

Print_ISBN

0-7803-0760-7

Type

conf

DOI

10.1109/TEST.1992.527836

Filename

527836