Title :
Co-optimizing process development, layout and circuit design for cost-effective 22nm technology platform
Author_Institution :
PDF Solutions, Inc., San Jose, CA, USA
Abstract :
The economic and technological challenges of process development are threatening the timely availability of advanced nodes. Meanwhile design and product organizations are demanding the continued delivery of Moore´s law density scaling to justify node migration. Balancing the requirements of design with the capabilities and physical limitations of advanced processes will require capitalizing on opportunities for co-optimization between process development, layout and circuit design. In this presentation, we will examine the challenges and highlight the opportunities for achieving an economically feasible path to 22 nm.
Keywords :
integrated circuit layout; nanoelectronics; Moore law density scaling; circuit design; circuit layout; cooptimizing process development; cost-effective technology platform; node migration; size 22 nm; Circuit synthesis; Delay effects; Fitting; High K dielectric materials; High-K gate dielectrics; Moore´s Law; Product design; SPICE; Silicon; Systematics;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424325
