• DocumentCode
    1652077
  • Title

    Design challenges for 22nm CMOS and beyond

  • Author

    Borkar, Shekhar

  • Author_Institution
    Intel Corp., Hillsboro, OR, USA
  • fYear
    2009
  • Firstpage
    1
  • Lastpage
    1
  • Abstract
    This paper presents technology and economic challenges posed by 22 nm CMOS and beyond. They can be addressed by advances in design technology, methodology, validation, and testing, to continue to enjoy the benefits of CMOS scaling in the future, as we have over the past decades.
  • Keywords
    CMOS integrated circuits; electronic design automation; integrated circuit design; CMOS scaling; automated design methodology; economic challenges; integrated circuit design; size 22 nm; CMOS technology; Cost function; Degradation; Design methodology; Design optimization; Hardware; Manufacturing; Paper technology; Power generation economics; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting (IEDM), 2009 IEEE International
  • Conference_Location
    Baltimore, MD
  • Print_ISBN
    978-1-4244-5639-0
  • Electronic_ISBN
    978-1-4244-5640-6
  • Type

    conf

  • DOI
    10.1109/IEDM.2009.5424329
  • Filename
    5424329
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1652077