DocumentCode

1652185

Title

A Graph Theoretic Approach to Partial Scan Design by K-Cycle Elimination

Author

Park, Sungju ; Akers, Sheldon B.

fYear

1992

Firstpage

303

Keywords

Circuit testing; Delay; Feedback; Flip-flops; Hardware; NP-complete problem; Sequential analysis; Sequential circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1992. Proceedings., International

ISSN

1089-3539

Print_ISBN

0-7803-0760-7

Type

conf

DOI

10.1109/TEST.1992.527837

Filename

527837