Leakage Power Dependent Temperature Estimation to Predict Thermal Runaway in FinFET Circuits

In this work, we propose a methodology to self-consistently solve leakage power with temperature to predict thermal runaway. We target 28nm FinFET based circuits as they are more prone to thermal runaway compared to bulk-MOSFETs. We generate thermal models for logic cells to self-consistently determine the temperature map of a circuit block. Our proposed condition for thermal runaway shows the design trade off between the primary input (PI) activity of a circuit block, sub-threshold leakage at the room temperature and the thermal resistance of the package. We show that in FinFET circuits, thermal runaway can occur at the ITRS specified sub-threshold leakage (150nA/mum, high-performance) for a nominal PI activity of 0.5 and typical package thermal resistance