DocumentCode
1652267
Title
New approach of 90nm low-k interconnect evaluation using a voltage ramp dielectric breakdown (VRDB) test
Author
Aubel, Oliver ; Kiene, Michael ; Yao, Walter
Author_Institution
AMD Saxony, Germany
fYear
2005
Firstpage
483
Lastpage
489
Keywords
Poole-Frenkel effect; dielectric measurement; electric breakdown; extrapolation; integrated circuit interconnections; integrated circuit measurement; integrated circuit modelling; integrated circuit reliability; 90 nm; BEoL-TDDB test; BTS; Poole-Frenkel equation; VRDB test; bias temperature stress test; breakdown voltage distribution extrapolation model; diffusion driven effects; failure mechanisms; gate-oxide-like failures; low temperature dependence; low-k interconnect; minimum space dielectric areas; product lifetime prediction; reliability; time dependant dielectric breakdown; voltage acceleration; voltage ramp dielectric breakdown test; Breakdown voltage; Copper; Dielectric breakdown; Dielectric materials; Dielectric measurements; Electric breakdown; Integrated circuit interconnections; Stress; Temperature measurement; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International
Print_ISBN
0-7803-8803-8
Type
conf
DOI
10.1109/RELPHY.2005.1493133
Filename
1493133
Link To Document