Title :
Technologies to further reduce soft error susceptibility in SOI
Author :
Oldiges, P. ; Dennard, R. ; Heidel, D. ; Ning, T. ; Rodbell, K. ; Tang, H. ; Gordon, M. ; Wissel, L.
Author_Institution :
Syst. & Technol. Group, IBM Corp., Hopewell Junction, NY, USA
Abstract :
Methods for soft error rate reduction in silicon on insulator devices and circuits are explored and evaluated via simulations that have been validated against hardware measurements. Our methodology is first introduced, and the following techniques are examined in detail: 1) Body thinning, 2) carrier lifetime reduction, 3) body contacts, 4) stacked devices, and 5) parallel devices. Finally, the advantages and disadvantages of all methods are described.
Keywords :
radiation hardening (electronics); silicon-on-insulator; body contacts; body thinning; carrier lifetime reduction; silicon-on-insulator; soft error susceptibility; stacked devices; Bipolar transistors; Charge carrier lifetime; Charge measurement; Circuit simulation; Current measurement; Hardware; Random access memory; Research and development; Silicon on insulator technology; Single event upset;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424338
