Title :
Ultra thinning 300-mm wafer down to 7-µm for 3D wafer Integration on 45-nm node CMOS using strained silicon and Cu/Low-k interconnects
Author :
Kim, Y.S. ; Tsukune, A. ; Maeda, N. ; Kitada, H. ; Kawai, A. ; Arai, K. ; Fujimoto, K. ; Suzuki, K. ; Mizushima, Y. ; Nakamura, T. ; Ohba, T. ; Futatsugi, T. ; Miyajima, M.
Author_Institution :
Fujitsu Microelectron. Ltd., Mie, Japan
Abstract :
High performance 45-nm Node and its 3D integration employed aggressively thinned down to 7-μm of 300-mm wafer for the Wafer-on-a-Wafer (WOW) application has been succeeded for the first time. The impact of ultra thin wafer on strained transistors and Cu/low-k multilevel interconnects is described. Properties examined include Kelvin and stack chain resistances of Cu interconnects as well as Ion-Ioff, threshold voltage shift, and junction leakage of transistors. It was found that the electrical properties were not affected by bonding, thinning and debonding process indicating good feasibility of 3D stacking integration to the strain and low-k technology.
Keywords :
CMOS integrated circuits; copper; cryogenic electronics; integrated circuit interconnections; silicon; three-dimensional integrated circuits; wafer bonding; 3D stacking integration; 3D wafer integration; Cu; Kelvin resistance; Si; bonding; copper interconnects; debonding process; electrical properties; junction leakage; low-k interconnects; low-k technology; node CMOS; size 300 mm to 7 mum; size 45 nm; stack chain resistance; strained silicon; strained transistors; threshold voltage shift; ultra thinning wafer; wafer-on-a-wafer application; CMOS technology; Capacitive sensors; Etching; Leakage current; MOSFETs; Silicon; Thermal stresses; Threshold voltage; Through-silicon vias; Wafer bonding;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424349
