A study of linearizing techniques used in MOS analog multipliers

Author

Rueda, A. ; Acedo, M. ; Huertas, J.L.

Author_Institution

Dept. of Electron. & Electromagn., Sevilla Univ., Spain

fYear

1989

Firstpage

1437

Abstract

Two different transconductance linearization schemes are studied. By means of a simple saturation model, the ideal linear input range for each one is obtained and a comparative study is carried out. Using a more accurate model, analytical expressions are derived that yield an efficient design strategy to reduce the second-order effects. One of these cells has been used to design a four-quadrant multiplier fabricated in a 2-μm, 5-V process. An experimental linear input range of 1.4 V has been measured, showing the suitability of the circuit structure in a low-power process when the authors´ strategy is used

Keywords

MOS integrated circuits; analogue computer circuits; multiplying circuits; nonlinear network analysis; 1.4 V; 2 micron; 5 V; MOS analog multipliers; design strategy; four-quadrant multiplier; ideal linear input range; large signal static characteristics; low-power process; saturation model; second-order effects; transconductance linearization schemes; Circuit analysis; Coupling circuits; Differential amplifiers; MOSFETs; Performance analysis; Radio access networks; Signal analysis; Transconductance; Transconductors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100627

Filename

100627