3D stacked ICs using Cu TSVs and Die to Wafer Hybrid Collective bonding

Author

Katti, G. ; Mercha, A. ; Van Olmen, J. ; Huyghebaert, C. ; Jourdain, A. ; Stucchi, M. ; Rakowski, M. ; Debusschere, I. ; Soussan, P. ; Dehaene, W. ; De Meyer, K. ; Travaly, Y. ; Beyne, E. ; Biesemans, S. ; Swinnen, B.

Author_Institution

IMEC, Leuven, Belgium

fYear

2009

Firstpage

1

Lastpage

4

Abstract

In this paper we demonstrate functional 3D circuits obtained by a 3D Stacked IC approach using both Cu Through Silicon Vias (TSV) First and cost effective solution Die-to-Wafer Hybrid Collective bonding. The Cu TSV-First process is inserted between contact and M1. The top die is thinned down to 25 Â¿m and bonded to the landing wafer by Hybrid Bonding. Measurements and simulations of the power delay trade-offs of various 3D Ring Oscillator are provided as a demonstration of the relevance of such process route and of the design/simulation capabilities.

Keywords

copper; integrated circuit interconnections; oscillators; three-dimensional integrated circuits; wafer bonding; 3D ring oscillator; 3D stacked IC; Cu; TSV; die-to-wafer hybrid collective bonding; power delay trade-offs; size 25 mum; through silicon vias; Atherosclerosis; Cost function; Degradation; Delay; Integrated circuit interconnections; Silicon; Three-dimensional integrated circuits; Through-silicon vias; Very large scale integration; Wafer bonding;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424351

Filename

5424351