Performances improvement of FPGA using novel multilevel hierarchical interconnection structure

This paper presents a new multilevel hierarchical FPGA (MFPGA) architecture that unifies two unidirectional programmable networks: a predictible downward network based on the Butterfly-Fat-Tree topology, and an upward network using hierarchy. Studies based on the Rent´s Rule show that wiring and switch requirements in the MFPGA grow slower than in traditional topologies. New tools are developed to place and route several benchmark circuits on this architecture. Experimental results based on the MCNC benchmarks show that MFPGA can implement circuits with an average gain of 40% in total area compared with mesh architecture