Design of highly efficient VLSI architectures for 2-D DWT and 2-D IDWT

This paper presents a design methodology for the implementation of high-performance 2-D discrete wavelet transform (DWT) and 2-D inverse DWT (IDWT). By exploiting the multi-rate feature inherent in the algorithms, an effective schedule that interleaves all the row-wise and column-wise computations of different octaves onto three fundamental convolutional filters is proposed. Based on this computation schedule, very high efficient architectures can be synthesized. The resulting architectures cannot only achieve fast computation time at less silicon cost due to nearly full hardware utilization, but they are also simple and modular, making them very suitable for VLSI implementation. Furthermore, the proposed design methodology enables the design of the configurable architecture that can process both DWT and IDWT