Title :
Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications
Author :
Mookerjea, S. ; Mohata, D. ; Krishnan, R. ; Singh, J. ; Vallett, A. ; Ali, A. ; Mayer, T. ; Narayanan, V. ; Schlom, D. ; Liu, A. ; Datta, S.
Author_Institution :
Electr. Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
Vertical In0.53Ga0.47As tunnel field effect transistors (TFETs) with 100nm channel length and high-k/metal gate stack are demonstrated with high Ion/Ioff ratio (>104). At VDS = 0.75V, a record on-current of 20¿A/¿m is achieved due to higher tunneling rate in narrow tunnel gap In0.53Ga0.47As. The TFETs exhibit gate bias dependent NDR characteristics at room temperature under forward bias confirming band to band tunneling. The measured data are in excellent agreement with two-dimensional numerical simulation at all drain biases. A novel 6T TFET SRAM cell using virtual ground assist is demonstrated despite the asymmetric source/drain configuration of TFETs.
Keywords :
SRAM chips; field effect transistors; tunnel transistors; In0.53Ga0.47As; SRAM applications; TFET SRAM cell; channel length; drain biases; gate stack; low power logic; size 100 nm; tunneling rate; two-dimensional numerical simulation; vertical inter-band tunnel field effect transistors; virtual ground assist; voltage 0.75 V; Diodes; Doping; Electrostatic measurements; FETs; Gold; Logic; MOSFETs; Random access memory; Temperature; Tunneling;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424355
