DocumentCode
1652840
Title
Memory interconnection test at board level
Author
DeJong, F. ; deLindvanWijngaarden, A.J.
fYear
1995
Firstpage
328
Keywords
Algorithm design and analysis; Assembly; Circuit faults; Circuit testing; Integrated circuit interconnections; Logic devices; Logic testing; Pins; Random access memory; Surface-mount technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Conference, 1992. Proceedings., International
Conference_Location
Baltimore, MD
ISSN
1089-3539
Print_ISBN
0-7803-0760-7
Type
conf
DOI
10.1109/TEST.1992.527840
Filename
527840
Link To Document