• DocumentCode
    1652859
  • Title

    A Code Refinement Methodology for Performance-Improved Synthesis from C

  • Author

    Stitt, Greg ; Vahid, Frank ; Najjar, Walid

  • Author_Institution
    Dept. of Comput. Sci. & Eng., California Univ., Riverside, CA
  • fYear
    2006
  • Firstpage
    716
  • Lastpage
    723
  • Abstract
    Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffers due to the use of C constructs and coding practices that are not appropriate for hardware. Most previous approaches to addressing this problem require drastic changes to coding practice. We present an approach that instead requires only minimal changes but yields significant speedups. In this approach, a software developer initially writes C code as they normally would, and then applies simple refinement guidelines to only the performance-critical code regions, which are the regions most likely to be synthesized to hardware. Alternatively, if a designer is aware of performance-critical parts of the application, the guidelines could be followed during development. In this study, we analyze dozens of embedded benchmarks to determine the most common C coding practices that limit hardware performance, and introduce coding guidelines to make the code more amenable to synthesis. Those guidelines typically require minimal coding effort, generally consisting of less than ten lines of code for each guideline. The guidelines typically represent modifications that require designer knowledge, making the guidelines difficult or impossible for synthesis tools to automate. We apply these guidelines to six benchmarks, resulting in average speedups of 3.5times compared to synthesis from the original code with a negligible software size and performance overhead
  • Keywords
    C language; embedded systems; field programmable gate arrays; hardware-software codesign; C constructs; C language; FPGA; code refinement; embedded benchmarks; embedded systems; hardware synthesis; hardware-software partitioning; performance improved synthesis; performance-critical parts; software programming languages; synthesized hardware; Application software; Computer languages; Computer science; Embedded computing; Embedded software; Field programmable gate arrays; Guidelines; Hardware design languages; Permission; Software performance; FPGA; Synthesis; code refinement; coding guidelines; compilation; embedded systems; hardware/software partitioning;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2006. ICCAD '06. IEEE/ACM International Conference on
  • Conference_Location
    San Jose, CA
  • ISSN
    1092-3152
  • Print_ISBN
    1-59593-389-1
  • Electronic_ISBN
    1092-3152
  • Type

    conf

  • DOI
    10.1109/ICCAD.2006.320018
  • Filename
    4110257