Efficient implementation of low bit rate 1.6 Kbps speech coder using field programmable gate arrays

Author

Chen, Han-Chiang

Author_Institution

Adv. Technol. Center, Comput. & Commun. Labs., Ind. Technol. Res. Inst., Hsinchu, Taiwan

fYear

2001

fDate

6/23/1905 12:00:00 AM

Firstpage

161

Lastpage

168

Abstract

The cost-effective hardware architecture of a low bit rate 1.6 Kbit/s LPC (linear predictive coefficient)-based vocoder is proposed. The proposed architecture integrates both algorithms of the encoder and decoder. In the encoder, a simple finite state machine is presented to compute the autocorrelation function of speech. At the decoder side, efficient circuits are designed to transfer LSP (lne spectrum pair) to LPC. Only 29000 gate counts of XILINX XC4036XL FPGA are used to implement the vocoder

Keywords

correlation methods; field programmable gate arrays; finite state machines; linear predictive coding; speech coding; vocoders; 1.6 Kbit/s; LPC; LSP; XILINX XC4036XL; autocorrelation function; decoder; encoder; field programmable gate arrays; finite state machine; hardware architecture; line spectrum pair; linear predictive coefficient; speech coder; vocoder; Autocorrelation; Automata; Bit rate; Circuits; Computer architecture; Decoding; Hardware; Linear predictive coding; Speech; Vocoders;

fLanguage

English

Publisher

ieee

Conference_Titel

Signal Processing Systems, 2001 IEEE Workshop on

Conference_Location

Antwerp

ISSN

1520-6130

Print_ISBN

0-7803-7145-3

Type

conf

DOI

10.1109/SIPS.2001.957343

Filename

957343