Title :
Implementation of an efficient FIR filter chip for PRML read channels
Author :
Kang, Jin Y. ; Jo, Byung G. ; Sunwoo, Myung H.
Author_Institution :
Sch. of Electron. Eng., Ajou Univ., Suwon, South Korea
fDate :
6/23/1905 12:00:00 AM
Abstract :
This paper proposes a low power and area efficient FIR filter chip for partial-response maximum likelihood (PRML) disk drive read channels, which is a 6-b, 8-tap digital FIR filter. The proposed filter employs a parallel processing architecture and consists of four pipeline stages. It uses the modified Booth algorithm for multiplication and compressor logic for addition. CMOS pass-transistor logic is used for low power consumption and single-rail logic is used to reduce the chip area. The proposed filter chip, using the 0.65 μm technology, dissipates 120 mW at 100 Hz, uses the 3.3 V power supply and occupies 1.88×1.38 mm 2. The chip shows about 11% power reduction and about 15% area reduction compared with existing architectures. This chip was fabricated by Hyundai Semiconductor
Keywords :
CMOS logic circuits; FIR filters; digital arithmetic; digital filters; disc drives; integrated circuit design; parallel architectures; partial response channels; pipeline processing; power consumption; 0.65 micron; 1.38 mm; 1.88 mm; 100 Hz; 120 mW; 3.3 V; Booth algorithm; CMOS pass-transistor logic; Hyundai Semiconductor; PRML disk drive read channels; addition; chip area reduction; compressor logic; digital filter; efficient FIR filter chip; low power consumption; multiplication; parallel processing architecture; partial-response maximum likelihood read channels; pipeline stages; single-rail logic; Adaptive equalizers; Adders; CMOS logic circuits; CMOS technology; Disk drives; Energy consumption; Finite impulse response filter; Parallel processing; Pipelines; Power engineering and energy;
Conference_Titel :
Signal Processing Systems, 2001 IEEE Workshop on
Conference_Location :
Antwerp
Print_ISBN :
0-7803-7145-3
DOI :
10.1109/SIPS.2001.957348
