Title :
Challenges and solutions of FinFET integration in an SRAM cell and a logic circuit for 22 nm node and beyond
Author :
Kawasaki, H. ; Basker, V.S. ; Yamashita, T. ; Lin, C.H. ; Zhu, Y. ; Faltermeier, J. ; Schmitz, S. ; Cummings, J. ; Kanakasabapathy, S. ; Adhikari, H. ; Jagannathan, H. ; Kumar, A. ; Maitra, K. ; Wang, J. ; Yeh, C.-C. ; Wang, C. ; Khater, M. ; Guillorn, M.
Author_Institution :
IBM Res. at Albany Nanotech, Toshiba America Electron. Components Inc., Albany, NY, USA
Abstract :
FinFET integration challenges and solutions are discussed for the 22 nm node and beyond. Fin dimension scaling is presented and the importance of the sidewall image transfer (SIT) technique is addressed. Diamond-shaped epi growth for the raised source-drain (RSD) is proposed to improve parasitic resistance (Rpara) degraded by 3-D structure with thin Si-body. The issue of Vt -mismatch is discussed for continuous FinFET SRAM cell-size scaling.
Keywords :
CMOS logic circuits; CMOS memory circuits; SRAM chips; elemental semiconductors; epitaxial growth; semiconductor growth; silicon; system-on-chip; three-dimensional integrated circuits; FinFET integration; SRAM Cell; Si; diamond-shaped epitaxial growth; fin dimension scaling; logic circuit; parasitic resistance degredation; raised source-drain; sidewall image transfer technique; size 22 nm; Costs; Degradation; Electronic components; Electrostatics; FETs; FinFETs; Ion implantation; Logic circuits; Random access memory; Sputtering;
Conference_Titel :
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location :
Baltimore, MD
Print_ISBN :
978-1-4244-5639-0
Electronic_ISBN :
978-1-4244-5640-6
DOI :
10.1109/IEDM.2009.5424366
