1653097

Design on power-rail esd clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-NM CMOS process

Ker, Ming-Dou ; Chen, Wen-Yi ; Hsu, Kuo-Chun

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

2005

606

607

CMOS integrated circuits; MIS devices; electrostatic discharge; integrated circuit design; integrated circuit reliability; semiconductor device reliability; 1 V; 130 nm; 2.5 V; 3.3 V; CMOS process; ESD detection circuit; IC product reliability; electrostatic discharge; gate-oxide reliability; pMOS devices; power-rail ESD clamp circuit design; stacked nMOS devices; CMOS process; CMOS technology; Circuits; Clamps; Electrostatic discharge; Laboratories; Nanoelectronics; Power system protection; Threshold voltage; Variable structure systems;

English

ieee

Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

0-7803-8803-8

conf

10.1109/RELPHY.2005.1493165

1493165