DocumentCode
1653119
Title
A 25-nm gate-length FinFET transistor module for 32nm node
Author
Chang, Chang-Yun ; Lee, Tsung-Lin ; Wann, Clement ; Li-Shyue Lai ; Chen, Hung-Ming ; Yeh, Chin-Chieh Yeh ; Chang, Chin-Sheng ; Ho, Chia-Cheng ; Sheu, Jyh-Cheng ; Kwok, Tsz-Mei ; Feng Yuan ; Yu, Shao-Ming ; Hu, Chia-Feng ; Shen, Jeng-Jung ; Liu, Yi-Hsuan ;
Author_Institution
R&D, Taiwan Semicond. Manuf. Co., Hsinchu, Taiwan
fYear
2009
Firstpage
1
Lastpage
4
Abstract
FinFET is the most promising double-gate transistor architecture to extend scaling over planar device. We present a high-performance and low-power FinFET module at 25 nm gate length. When normalized to the actual fin perimeter, N-FinFET and P-FinFET have 1200 and 915 ??A/??m drive current respectively at 100 nA/??m leakage under 1V. To our knowledge this is the best FinFET drive current at such scaled gate length. This scaled gate length enables this FinFET transistor for 32 nm node insertion. With aggressive fin pitch scaling, the effective transistor width is approximately 1.9X and 2.7X over planar for typical logic and SRAM on the same layout area (i.e., silicon real estate). Due to superior electrostatics and reduced random dopant fluctuation, this high drive current can be readily traded with VDD scaling for low power.
Keywords
MOSFET; SRAM chips; FinFET drive current; FinFET transistor module; SRAM; double-gate transistor architecture; fin pitch scaling; gate length; random dopant fluctuation; size 25 nm; size 32 nm; transistor width; Capacitive sensors; Electrostatics; Etching; FinFETs; Fluctuations; Implants; Logic; Random access memory; Semiconductor device manufacture; Silicon;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting (IEDM), 2009 IEEE International
Conference_Location
Baltimore, MD
Print_ISBN
978-1-4244-5639-0
Electronic_ISBN
978-1-4244-5640-6
Type
conf
DOI
10.1109/IEDM.2009.5424367
Filename
5424367
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