45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell

Author

Lin, YiChing ; Kang, S.H. ; Wang, Y.J. ; Lee, K. ; Zhu, X. ; Chen, W.C. ; Li, X. ; Hsu, W.N. ; Kao, Y.C. ; Liu, M.T. ; Chen, W.C. ; YiChing Lin ; Nowak, M. ; Yu, N. ; Tran, Luan

Author_Institution

Taiwan Semicond. Manuf. Co. Ltd., Hsinchu, Taiwan

fYear

2009

Firstpage

1

Lastpage

4

Abstract

This paper reports a 45 nm spin-transfer-torque (STT) MRAM embedded into a standard CMOS logic platform that employs low-power (LP) transistors and Cu/low-k BEOL. We believe that this is the first-ever demonstration of embedded STT MRAM that is fully compatible with the 45 nm logic technology. To ensure the switching margin, a novel "reverse-connection" 1T/1MT cell has been developed with a cell size of 0.1026 Â¿m². This cell is utilized to build embedded memory macros up to 32 Mbits in density. Device attributes and design windows have been examined by considering PVT variations to secure operating margins. Promising early reliability data on endurance, read disturb, and thermal stability have been obtained.

Keywords

CMOS logic circuits; MRAM devices; low-power electronics; Cu/low-k BEOL; complementary metal-oxide-semiconductor; embedded memory macros; endurance; low power CMOS logic; low power transistors; random access memory; read disturb; reliability; reverse connection; size 45 nm; spin transfer torque MRAM; thermal stability; CMOS logic circuits; CMOS technology; Logic devices; MOS devices; Magnetic tunneling; Nonvolatile memory; Pulp manufacturing; Scalability; Semiconductor device manufacture; Thermal stability;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting (IEDM), 2009 IEEE International

Conference_Location

Baltimore, MD

Print_ISBN

978-1-4244-5639-0

Electronic_ISBN

978-1-4244-5640-6

Type

conf

DOI

10.1109/IEDM.2009.5424368

Filename

5424368