Title :
VLSI architecture of a MPEG-4 visual renderer
Author :
Nguyen-Phuc, Quynh-Lien ; Sorolla, Carolina Miro
Author_Institution :
Philips Res. France, Suresnes, France
fDate :
6/23/1905 12:00:00 AM
Abstract :
This paper presents the architecture of a hardware block supporting the real-time rendering of all 2D natural or synthetic visual objects proposed by the MPEG-4 standard as well as sprite decoding. It is compliant to main profile, Level3 and hybrid visual profile. A software model allows us to validate the visual quality of the rendered scene. The complexity of this architecture is evaluated and the architectural choices are validated by means of simulations of a behavioral model
Keywords :
VLSI; code standards; decoding; multimedia computing; real-time systems; rendering (computer graphics); video coding; 2D visual objects; LeveI3; MPEG-4 standard; VLSI architecture; behavioral model; complexity evaluation; hybrid visual profile; main profile; real-time rendering; simulations; software model; sprite decoding; visual quality; visual renderer; Cost function; Decoding; Encoding; Hardware; Layout; MPEG 4 Standard; Sprites (computer); Transform coding; Very large scale integration; Video compression;
Conference_Titel :
Signal Processing Systems, 2001 IEEE Workshop on
Conference_Location :
Antwerp
Print_ISBN :
0-7803-7145-3
DOI :
10.1109/SIPS.2001.957358
