DocumentCode :
1653413
Title :
Fast isomorphism testing for a graph-based analog circuit synthesis framework
Author :
Meissner, Markus ; Mitea, Oliver ; Luy, Linda ; Hedrich, Lars
Author_Institution :
Dept. of Comput. Sci., Univ. of Frankfurt/Main, Frankfurt am Main, Germany
fYear :
2012
Firstpage :
757
Lastpage :
762
Abstract :
This contribution presents a major improvement for our analog synthesis framework with an explorative characteristic. The presented approach in principle allows the synthesis of a wide range of circuits, without the limitation to specific circuit classes. Defined by a specification of up to 15 different performances, a fully sized, transistor level circuit is synthesized for a provided process technology. The presented work reduces the needed computational effort and thus drastically reduces the synthesis time, while adding new abstraction into the framework to provide an even wider range of synthesized circuits - demonstrated in experimental results.
Keywords :
analogue integrated circuits; graph theory; integrated circuit design; integrated circuit testing; fast isomorphism testing; fully sized transistor level circuit synthesis; graph-based analog circuit synthesis framework; Algorithm design and analysis; Capacitors; Complexity theory; Partitioning algorithms; Runtime; Topology; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2012
Conference_Location :
Dresden
ISSN :
1530-1591
Print_ISBN :
978-1-4577-2145-8
Type :
conf
DOI :
10.1109/DATE.2012.6176570
Filename :
6176570
Link To Document :
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