Title :
An architecture for a radix-4 modular pipeline fast Fourier transform
Author :
El-Khashab, Ayman M. ; Swartzlander, Earl E., Jr.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
We present a radix-4 modular pipeline architecture for computing the discrete Fourier transform (DFT). For an N-point DFT, two conventional pipeline √N-point fast Fourier transform (FFT) modules are joined by a specialized center element. The center element contains memories, coefficient ROMs, multipliers, and control logic. Compared with a standard N-point pipeline FFT, the modular FFT significantly reduces the number of delay lines to 2√N. Further, the coefficient storage is concentrated within the center element, thereby reducing the ROM requirement within the pipeline FFT modules. The centralized memory and address generator provide data storage and reordering. The architecture has been analyzed through simulation and compared to the conventional pipeline FFT. The throughput of a standard radix-4 pipeline FFT is maintained with a slightly higher end-to-end latency. A reduction in power is achieved because the modular pipeline exhibits N/2 bit transitions on each clock as compared to y bit transitions in the conventional pipeline.
Keywords :
computer architecture; discrete Fourier transforms; pipeline processing; signal processing; DFT; centralized memory; coefficient storage; conventional pipeline FFT; data address generator; discrete Fourier transform; end-to-end latency; fast Fourier transform; radix-4 modular pipeline architecture; Analytical models; Clocks; Computer architecture; Delay lines; Discrete Fourier transforms; Fast Fourier transforms; Logic; Pipelines; Read only memory; Throughput;
Conference_Titel :
Application-Specific Systems, Architectures, and Processors, 2003. Proceedings. IEEE International Conference on
Print_ISBN :
0-7695-1992-X
DOI :
10.1109/ASAP.2003.1212861