Hardware implementation of an elliptic curve processor over GF(p)

Author

Örs, Siddika Berna ; Batina, Lejla ; Preneel, Bart ; Vandewalle, Joos

Author_Institution

ESAT/SCD-COSIC, Katholieke Univ., Leuven, Leuven-Heverlee, Belgium

fYear

2003

Firstpage

433

Lastpage

443

Abstract

We describe a hardware implementation of an arithmetic processor which is efficient for bit-lengths suitable for both commonly used types of public key cryptography (PKC), i.e., elliptic curve (EC) and RSA cryptosystems. Montgomery modular multiplication in a systolic array architecture is used for modular multiplication. The processor consists of special operational blocks for Montgomery modular multiplication, modular addition/subtraction, EC point doubling/addition, modular multiplicative inversion, EC point multiplier, projective to affine coordinates conversion and Montgomery to normal representation conversion.

Keywords

digital arithmetic; field programmable gate arrays; public key cryptography; systolic arrays; EC; FPGA; Montgomery modular multiplication; PKC; RSA cryptosystem; affine coordinates conversion; arithmetic processor; elliptic curve processor; hardware implementation; modular addition/subtraction; modular multiplicative inversion; normal representation conversion; operational block; point doubling/addition; point multiplier; projective coordinates; public key cryptography; systolic array architecture; Arithmetic; Delay; Elliptic curve cryptography; Elliptic curves; Energy consumption; Field programmable gate arrays; Galois fields; Hardware; Public key cryptography; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Application-Specific Systems, Architectures, and Processors, 2003. Proceedings. IEEE International Conference on

ISSN

2160-0511

Print_ISBN

0-7695-1992-X

Type

conf

DOI

10.1109/ASAP.2003.1212866

Filename

1212866