DSP parallel architecture for image compression

A DSP-based parallel architecture for image compression is presented. The basic processing module is built around a two DSP TMS 320C25 arrangement. These DSPs work in a parallel fashion over the different blocks of the partitioned image. The architecture is intended to perform transform coding of 256×256 8-bit images which are divided in n×n (n=4,8,16, . . .) squared blocks for processing tasks. The modular implementation of the system permits the use of a variable number of processing units in accordance with the needed throughput, giving the architecture real-time processing capabilities if necessary. Also presented is a proposal for architecture reconfiguration, which makes it capable of implementing second-generation image coding technique