1653701

Effect of layout orientation on the performance and reliabiltiy of high voltage N-LDMOS in standard submicron logic STI CMOS process

Wang, Bin ; Nguyen, Hoc ; Mavoori, J. ; Horch, Andy ; Ma, Yanjun ; Humes, Todd ; Paulsen, Ron

Impinj, Inc., Seattle, WA, USA

2005

654

655

hot carriers; isolation technology; leakage currents; power MOSFET; semiconductor device breakdown; semiconductor device reliability; 0.18 micron; 0.25 micron; 12 V; N-channel laterally diffused drain MOSFET; device drain current leakage; drain breakdown; high voltage N-LDMOS; hot-carrier injection reliability; layout orientation effects; logic STI CMOS; on-state current characteristics; standard CMOS process; CMOS logic circuits; CMOS process; FETs; Geometry; Human computer interaction; Isolation technology; Logic devices; Power control; Semiconductor device modeling; Voltage;

English

ieee

Reliability Physics Symposium, 2005. Proceedings. 43rd Annual. 2005 IEEE International

0-7803-8803-8

conf

10.1109/RELPHY.2005.1493189

1493189