On the extension of SystemC by SystemVerilog assertions

In this paper, we present an extension to the SystemC library by SystemVerilog assertions. SystemC is an emerging system level design and verification language based on C++ object oriented paradigms. It enables the modelling and simulation of a complete system-on-a-chip. We propose to extend the SystemC library with assertion based verification (ABV) which is a higher abstraction mechanism that allows a concise capturing of design specification. In order to do so, we consider the same ABV structure as defined for the SystemVerilog language. We propose to add ABV as SystemC monitors on top of the original design. Doing so, an important goal is achieved, namely a unified language which brings together enhanced design and assertion features that deliver increased designer productivity and smarter verification. In the same time, considering SystemVerilog´s standard assertions will take advantage from the result of an industry-wide effort to extend the Verilog language to include enhanced modelling and verification features.