Title :
A 1.0 GHz clock generator design with a negative delay using a single-shot locking method
Author :
Wang, Chua ; Tseng, Yih-Long ; Kao, Rong-Sui
Author_Institution :
Dept. of Electr. Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
fDate :
6/23/1905 12:00:00 AM
Abstract :
A high-speed digital clock generator circuit is presented to provide negative delays in order to avoid a multi-locking hazard. The negative delay also results in small power consumption and shorter access time if the proposed circuit is used in the clock generator circuit of memory devices. Meanwhile, an accurately locked clock signal is also provided. The locked clock signal can be as high as 1.0 GHz at the presence of a random noise with 10% of power supply voltage while the design is implemented by 0.35 μm CMOS 1P4M technology
Keywords :
CMOS digital integrated circuits; clocks; delay lock loops; high-speed integrated circuits; low-power electronics; pulse generators; synchronisation; timing circuits; 0.35 micron; 1 GHz; CMOS IP4M technology; DLL; accurately locked clock signal; digital clock generator circuit; high-speed clock generator; memory devices; multi-locking hazard; negative delays; power consumption; single-shot locking; CMOS technology; Circuit noise; Clocks; Delay effects; Energy consumption; Hazards; Power generation; Power supplies; Signal design; Voltage;
Conference_Titel :
Electronics, Circuits and Systems, 2001. ICECS 2001. The 8th IEEE International Conference on
Print_ISBN :
0-7803-7057-0
DOI :
10.1109/ICECS.2001.957413
